Jia Wang

Assistant Professor
Electrical and Computer Engineering
Illinois Institute of Technology

3301 South Dearborn Street, Siegel Hall
Chicago, IL 60208

E-mail: jwang at ece dot iit dot edu

Introduction

Dr. Wang received his B.S. degree from Department of Electronic Engineering at Tsinghua University, China, in 2002, and his M.S. and Ph.D. degrees from Department of Electrical Engineering and Computer Science at Northwestern University in 2005 and 2008, respectively.

Vita

Research

Dr. Wang's research interest is on design automation of VLSI circuits and large scale computing systems, where algorithms and methodologies are developed to overcome the system complexity and the silicon complexity such that the correctness and the efficiency of the systems are guaranteed. He is also interested in general algorithm and mechanism design that would apply to fields beyond VLSI CAD.

Courses

Publications

The papers here are copyrighted by the corresponding organizations. They have been made available as a courtesy.

    Journal articles

  1. C. Lin, Jia Wang, and H. Zhou, Clustering for Processing Rate Optimization. IEEE Transactions on VLSI Systems, 14(11), pp. 1264-1275, Nov. 2006.
  2. Jia Wang and H. Zhou, Optimal Jumper Insertion for Antenna Avoidance Considering Antenna Charge Sharing. IEEE Transactions on Computer-Aided Design, 26(8), pp. 1445-1453, Aug. 2007.
  3. Z. Gu, Jia Wang, R. P. Dick, and H. Zhou, Unified Incremental Physical-Level and High-Level Synthesis. IEEE Transactions on Computer-Aided Design, 26(9), pp. 1576-1588, Sep. 2007.
  4. Jia Wang, D. Das, and H. Zhou, Gate Sizing by Lagrangian Relaxation Revisited. IEEE Transactions on Computer-Aided Design, 28(7), pp. 1071-1084, Jul. 2009.
  5. W. Xu, Jia Wang, Y. Hu, J.-Y. Lee, L. He, and M. Sarrafzadeh, In-Place FPGA Retiming for Mitigation of Variational Single-Event Transient Faults. IEEE Transactions on Circuits and Systems I, 58(6), pp. 1372-1381, Jun. 2011.
  6. X. Xiong and Jia Wang, Dual Algorithms for Vectorless Power Grid Verification under Linear Current Constraints. IEEE Transactions on Computer-Aided Design, 30(10), pp. 1469-1482, Oct. 2011.
  7. C. Wang, K. Ren, Jia Wang, and Q. Wang, Harnessing the Cloud for Securely Outsourcing Large-Scale Systems of Linear Equations. To appear, IEEE Transactions on Parallel and Distributed Systems.
  8. J. Wu, Jia Wang, K. Li, H. Zhou, Q. Lv, L. Shang, and Y. Sun, Large-Scale Energy Storage System Design and Optimization for Emerging Electric-Drive Vehicles. To appear, IEEE Transactions on Computer-Aided Design.

    9. Refereed conference papers

  9. Jia Wang and H. Zhou, Minimal Period Retiming under Process Variations. Great Lake Symposium on VLSI, Boston, MA, 2004.  (poster)
  10. H. Zhou and Jia Wang, ACG--Adjacent Constraint Graph for General Floorplans. IEEE International Conference on Computer Design, San Jose, CA, 2004.  (talk)
  11. Jia Wang and H. Zhou, Interconnect Estimation Without Packing via ACG Floorplans. Asia and South Pacific Design Automation Conference, Shanghai, China, 2005.  (poster)
  12. Z. Gu, Jia Wang, R. P. Dick, and H. Zhou, Incremental Exploration of the Combined Physical and Behavioral Design Space. ACM/IEEE Design Automation Conference, Anaheim, CA, 2005.
  13. C. Lin, Jia Wang, and H. Zhou, Clustering for Processing Rate Optimization. IEEE/ACM International Conference on Computer-Aided Design, San Jose, CA, 2005.  (Technical Report TR-NUCAD-2005-02)
  14. Z. P. Gu, Y. Yang, Jia Wang, R. P. Dick, and L. Shang, TAPHS: Thermal-Aware Unified Physical-Level and High-Level Synthesis. Asia and South Pacific Design Automation Conference, 2006. (One of eight best paper award nominees out of 432 submitted papers.)
  15. Jia Wang, P. Wu, and H. Zhou, Processing Rate Optimization by Sequential System Floorplanning. International Symposium on Quality Electronic Design, San Jose, CA, 2006.  (poster)
  16. Jia Wang and H. Zhou, Optimal Jumper Insertion for Antenna Avoidance under Ratio Upper-Bound. ACM/IEEE Design Automation Conference, San Francisco, CA, 2006.  (talk)  (benchmarks)
  17. N. Liveris, C. Lin, Jia Wang, H. Zhou, and P. Banerjee, Retiming for Synchronous Data Flow Graphs. Asia and South Pacific Design Automation Conference, 2007.
  18. Jia Wang, M.-Y. Kao, and H. Zhou, Address Generation for Nanowire Decoders. ACM Great Lakes Symposium on VLSI, Stresa, Italy, 2007.  (poster)
  19. Jia Wang, D. Das, and H. Zhou, Gate Sizing by Lagrangian Relaxation Revisited. IEEE/ACM International Conference on Computer-Aided Design, San Jose, CA, 2007.  (talk)
  20. Jia Wang and H. Zhou, An Efficient Incremental Algorithm for Min-Area Retiming. ACM/IEEE Design Automation Conference, Anaheim, CA, 2008.  (talk)  (benchmarks)
  21. Jia Wang and H. Zhou, Linear Constraint Graph for Floorplan Optimization with Soft Blocks. IEEE/ACM International Conference on Computer-Aided Design, San Jose, CA, 2008.  (talk)
  22. Jia Wang and H. Zhou, Exploring Adjacency in Floorplanning. Asia and South Pacific Design Automation Conference, Yokohama, Japan, 2009.  (talk)
  23. Jia Wang and H. Zhou, Risk Aversion Min-Period Retiming under Process Variations. Asia and South Pacific Design Automation Conference, Yokohama, Japan, 2009.  (talk)
  24. X. Yuan and Jia Wang, Statistical Timing Verification for Transparently Latched Circuits through Structural Graph Traversal. Asia and South Pacific Design Automation Conference, Taiwan, 2010.
  25. D. Das, Jia Wang, and H. Zhou, iRetILP: An Efficient Incremental Algorithm for Min-Period Retiming under General Delay Model. Asia and South Pacific Design Automation Conference, Taiwan, 2010.
  26. X. Xiong and Jia Wang, An Efficient Dual Algorithm for Vectorless Power Grid Verification under Linear Current Constraints. ACM/IEEE Design Automation Conference, Anaheim, CA, 2010.  (benchmarks)
  27. X. Xiong and Jia Wang, A Hierarchical Matrix Inversion Algorithm for Vectorless Power Grid Verification. IEEE/ACM International Conference on Computer-Aided Design, San Jose, CA, 2010.
  28. C. Wang, K. Ren, and Jia Wang, Secure and Practical Outsourcing of Linear Programming in Cloud Computing. IEEE International Conference on Computer Communications, Shanghai, China, 2011.
  29. C. Wang, K. Ren, Jia Wang, and K. Mahendra Raje Urs, Harnessing the Cloud for Securely Solving Large-scale Systems of Linear Equations. IEEE International Conference on Distributed Computing Systems, Minneapolis, MN, 2011.
  30. X. Xiong and Jia Wang, Vectorless Verification of RLC Power Grids with Transient Current Constraints. IEEE/ACM International Conference on Computer-Aided Design, San Jose, CA, 2011.  (talk)
  31. Jia Wang, Deterministic Random Walk Preconditioning for Power Grid Analysis. To appear, IEEE/ACM International Conference on Computer-Aided Design, 2012

    32. Invited papers

  32. Jia Wang, K. Li, Q. Lv, H. Zhou, and L. Shang, Hybrid Energy Storage System Integration for Vehicles. International Symposium on Low Power Electronics and Design, Austin, TX, 2010.
  33. X. Xiong and Jia Wang, Parallel Forward and Back Substitution for Efficient Power Grid Simulation. To appear, IEEE/ACM International Conference on Computer-Aided Design, 2012

Activities

Students

Dr. Wang is current recruiting students to join his research group. Financial support will be provided to qualified Ph.D students.

Researches in design automation/VLSI CAD provide necessary tools for the design of VLSI chips. Though device technology may evolve, CAD techniques will remain essential to organize individual devices into efficient and effective systems and to automate the tasks of system analysis, verification, and optimization.

Since the research work requires not only theoretical algorithmic advances but also efficient practical software implementations, students will be trained to achieve a good balance between mathematical reasoning and software development skills. Such training will prepare students for EDA tool vendors or any career requiring strong quantitative and programming skills.

Though not required, knowledge of combinatorics, optimization algorithms (linear programming, convex programming, etc.), and C++/STL will be a plus for the applicants.