Jia Wang Assistant Professor Electrical and Computer Engineering Illinois Institute of Technology 3301 South Dearborn Street, Siegel Hall Chicago, IL 60208 E-mail: jwang at ece dot iit dot edu

Introduction

Dr. Wang received his B.S. degree from Department of Electronic Engineering at Tsinghua University, China, in 2002, and his M.S. and Ph.D. degrees from Department of Electrical Engineering and Computer Science at Northwestern University in 2005 and 2008, respectively.

Vita

Research

Dr. Wang's research interest is on design automation of VLSI circuits and large scale computing systems, where algorithms and methodologies are developed to overcome the system complexity and the silicon complexity such that the correctness and the efficiency of the systems are guaranteed. He is also interested in general algorithm and mechanism design that would apply to fields beyond VLSI CAD.

Courses

• ECE 429 Introduction to VLSI Design (Fall 2008)
• ECE 585 Advanced Computer Architecture (Spring 2009)
• ECE 587 Hardware/Software Co-Design (Fall 2009)

Publications

Journal articles

1. C. Lin, Jia Wang, and H. Zhou, Clustering for Processing Rate Optimization. IEEE Transactions on VLSI Systems, 14(11), pp. 1264-1275, Nov. 2006.
2. Jia Wang and H. Zhou, Optimal Jumper Insertion for Antenna Avoidance Considering Antenna Charge Sharing. IEEE Transactions on Computer-Aided Design, 26(8), pp. 1445-1453, Aug. 2007.
3. Z. Gu, Jia Wang, R. P. Dick, and H. Zhou, Unified Incremental Physical-Level and High-Level Synthesis. IEEE Transactions on Computer-Aided Design, 26(9), pp. 1576-1588, Sep. 2007.

Refereed conference papers

4. Jia Wang and H. Zhou, Minimal Period Retiming under Process Variations. Great Lake Symposium on VLSI, Boston, MA, 2004.  (poster)
5. H. Zhou and Jia Wang, ACG--Adjacent Constraint Graph for General Floorplans. IEEE International Conference on Computer Design, San Jose, CA, 2004.  (talk)
6. Jia Wang and H. Zhou, Interconnect Estimation Without Packing via ACG Floorplans. Asia and South Pacific Design Automation Conference, Shanghai, China, 2005.  (poster)
7. Z. Gu, Jia Wang, R. P. Dick, and H. Zhou, Incremental Exploration of the Combined Physical and Behavioral Design Space. ACM/IEEE Design Automation Conference, Anaheim, CA, 2005.
8. C. Lin, Jia Wang, and H. Zhou, Clustering for Processing Rate Optimization. IEEE/ACM International Conference on Computer-Aided Design, San Jose, CA, 2005.  (Technical Report TR-NUCAD-2005-02)
9. Z. P. Gu, Y. Yang, Jia Wang, R. P. Dick, and L. Shang, TAPHS: Thermal-Aware Unified Physical-Level and High-Level Synthesis. Asia and South Pacific Design Automation Conference, 2006. (One of eight best paper award nominees out of 432 submitted papers.)
10. Jia Wang, P. Wu, and H. Zhou, Processing Rate Optimization by Sequential System Floorplanning. International Symposium on Quality Electronic Design, San Jose, CA, 2006.  (poster)
11. Jia Wang and H. Zhou, Optimal Jumper Insertion for Antenna Avoidance under Ratio Upper-Bound. ACM/IEEE Design Automation Conference, San Francisco, CA, 2006.  (talk)  (benchmarks)
12. N. Liveris, C. Lin, Jia Wang, H. Zhou, and P. Banerjee, Retiming for Synchronous Data Flow Graphs. Asia and South Pacific Design Automation Conference, 2007.
13. Jia Wang, M.-Y. Kao, and H. Zhou, Address Generation for Nanowire Decoders. ACM Great Lakes Symposium on VLSI, Stresa, Italy, 2007.  (poster)
14. Jia Wang, D. Das, and H. Zhou, Gate Sizing by Lagrangian Relaxation Revisited. IEEE/ACM International Conference on Computer-Aided Design, San Jose, CA, 2007.  (talk)
15. Jia Wang and H. Zhou. An Efficient Incremental Algorithm for Min-Area Retiming. ACM/IEEE Design Automation Conference, Anaheim, CA, 2008.  (talk)  (benchmarks)
16. Jia Wang and H. Zhou. Linear Constraint Graph for Floorplan Optimization with Soft Blocks. IEEE/ACM International Conference on Computer-Aided Design, San Jose, CA, 2008.  (talk)
17. Jia Wang and H. Zhou. Exploring Adjacency in Floorplanning. To appear, Asia and South Pacific Design Automation Conference, 2009.
18. Jia Wang and H. Zhou. Risk Aversion Min-Period Retiming under Process Variations. To appear, Asia and South Pacific Design Automation Conference, 2009.

Activities

ACG Floorplanner

• The ACG Floorplanner is maintained here.
  This floorplanner has been used in many collaborated research works.

Students

Dr. Wang is current recruiting students to join his research group. Financial support will be provided to qualified Ph.D students.

Researches in design automation/VLSI CAD provide necessary tools for the design of VLSI chips. Though device technology may evolve, CAD techniques will remain essential to organize individual devices into efficient and effective systems and to automate the tasks of system analysis, verification, and optimization.

Since the research work requires not only theoretical algorithmic advances but also efficient practical software implementations, students will be trained to achieve a good balance between mathematical reasoning and software development skills. Such training will prepare students for EDA tool vendors or any career requiring strong quantitative and programming skills.

Though not required, knowledge of combinatorics, optimization algorithms (linear programming, convex programming, etc.), and C++/STL will be a plus for the applicants.