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    Publications (2008 – 2011)  - Updated 09/09/2011

    Journal Publications (2008 – 2011, , After Joining IIT)

  1.  Kyung Ki Kim, Haiqing Nan, and Ken Choi, "Ultra-Low Power Gating Structure Using Low Threshold Voltage", IEEE Transactions on Circuits and Systems II, Vol. 56, Issue 12, pp926-930, Dec. 2009
  2. Yu-Chi Tsao and Ken Choi, "Area-Efficient Parallel FIR Digital Filter Structures For Symmetric Convolutions Based on Fast FIR Algorithm: IEEE Transactions on VLSI, ISSN: 1063-8210, Dec. 2010
  3. Kyung Ki Kim, Seong Mo Park, and Ken Choi, "On-Chip Aging Sensor Sircuits for Reliable Nanoscale MOSFET Circuits", IEEE Transactions on Circuits and Systems II, Vol. 57, Issue:10, pp.798-802, Oct. 2010
  4. Kyung Ki Kim and Ken Choi, "Hybrid CMOS and CNFET Power Gating in Ultra-Low Voltage Design", IEEE Transactions on Nanotechnology. 2011
  5. Haiqing Nan and Ken Choi, "TDDB Mornitoring and Compensation Circuit Design for Deeply Scaled CMOS Technology", IEEE Transactions on Device and Material Reliability, 2011
  6. Kyung Ki Kim and Ken Choi, "On-Chip Process Variation Mornitoring Circuit based on Gate Leakage Sensing", IET Electronics Letters, Vol. 46, Issue 3, pp.227-228, Feb. 2010
  7. Kyung Ki Kim and Ken Choi, "Power Grid Aware Tiing Analysis Using S-parameter", International Journal of Electronics, Vol 97 issue 7, pp.759-772, July. 2010
  8. Chongdu Cho and Ken Choi, "An Inscribed Surface Model for the Elastic Properties of Armchair Carbon Nanotubes", Journal of Mechanical Science and Technology, Springer, Vol 24, pp. 2233-2239, Jul. 2010
  9. Chongdu Cho and Ken Choi, "Effect of Bipolar Plate Materials on the Stress Distribution and Interfacial Contact Resistance in PEM Fuel Cell, "International Journal of Precision Engineering and Manufacturing, Springer, Vol.11, No.4, August 2010
  10. Kyung Ki Kim and Ken Choi, "Power Gating for Ultra-Low Voltage Circuits", International Journal of Electronics Letter, (Accepted) to be appeared in early 2011
  11. Haiqing Nan, Kyung Ki Kim, Wei Wang and Ken Choi, "Dynamic Voltage and Frequency Scaling for Power-Constrained Design using Process Voltage and Temperature Sensor Circuits", Journal of Information Processing System, March 31, 2011, pp. 93-102
  12. Li Li and Ken Choi, "Activity driven optimized bus specific clock gating for ultra-low-power smart space applications", IET communications, (Accepted) to be appeared in 2011
  13. Sheng Lu, Chongdu Cho, Kyu-won Choi, Wonjun Choi, Sangkyo Leeand Na Wang, "An inscribed surface model for the elastic properties of armchair carbon nanotube, "Journal of Mechanical Science and Technology, Volume 24, Number 11, PP. 2233-2239, July 2010
  14. Jaeik Cho, Manhyun Chung, Ken Choi, Yangsun Lee, Jongsub Moon, "Enhanced Security Protocols for EPC Global Gen2 on Smart Grid Network, "International Journal of Sensors, (Accepted) to be appeared in 2011
  15. Jaeik Cho, Ho Joon Lee, Ken Choi, Sangyep Nam, Jongsub Moon, "Visualization of Abnormal Behavior Detection using Parallel Coordinate and Correspondence Analysis, "International Journal of Information, (Accepted) to be appeard in 2011
  16. Jaeik Cho, Kyuwon Choi, Taeshik Shon, Jongsub Moon, "Enhanced Network Data Set Modeling Method and Its Evaluation Using MIT/LL Data Set", (Accepted) will be published in the 5th Supercomputing Journal
  17. Haiqing Nan, Ken Choi, "Novel radiation hardened latch design considering process, voltage and temperature variations for nanoscale CMOS technology", Journal of Microelectronics Reliability, In Press, Corrected Proof, Available online 9 August 2011, ISSN 0026-2714, DOI:10.1016/j.microrel.2011.07.048
  18. Yu-Chi Tsao and Ken Choi, "Cost-Reduced high speed architecture for Lattice Digital Filters based on cut-set localization", IJIPT (International Journal of Internet Protocol Technology), 2011
  19. Li Li and Ken Choi, "Energy Efficient Encoder Design of Distributed Video Coding for Wireless Video Sensor Network", INFORMATION, 2011
  20. Haiqing Nan and Ken Choi, "Hardened latch design for deeply scaled CMOS technology", INFORMATION, 2011
  21. Heung-Shik Lee, Chongdu Cho, Alan T. Zehnder and Kyu-won Choi, "Development of micromagnetostrictive wireless controllable actuator", J. Appl Phys. 109, 07E501 (2011); doi:10.1063/1.3536525

Conference Publications (2008 – 2011, After Joining IIT)

  1. NamSung Kim and Ken Choi, and et al., "Frequency and Yield Optimization using Power Gates in Power-Constrained Designs", IEEE-ACM ISLPED (International Symposium on Low Power Electronics and Design 2009), San Francisco, CA, August 19-21, 2009
  2. Li Li and Ken Choi, "Selective Power Gating using Wasting Toggle Rate for Ultra-Low Power Processor Design", IEEE EIT, p64-69, Ontario, Canada, 2009
  3. Feng Ge, Pranjal Jain and Ken Choi, "Ultra-Low Power and High Speed Design and Implementation of AES and SHA1 Hardware Cores in 65 Nanometer CMOS Technology", IEEE EIT, p127-132, Ontario, Canada, 2009
  4. Haiqing Nan and Ken Choi, "Inter-Hierarchical Power Analysis Methodology to Reduce Multiple Orders of Magnitude Run-Time without Compromising Accuracy", IEEE International SoC Design Conference, pp.556-559, November, 24. 2009 (Best Paper Award)
  5. Li Li, Ken Choi, Seongmo Park and Moo-Kyoung Chung, "Novel RT level methodology for low power by using wasting toggle rate based clock gating",  IEEE International SoC Design Conference, pp.484-487, November, 24. 2009
  6. Feng Ge and Ken Choi, "High Sensitivity UHF RFID Reader Baseband Design for EPC Class-1 Generation-2", RFID Conference, April 14-16, 2010
  7. Feng Ge and Ken Choi, "Novel Design and Implementation for High Sensitive Baseband Protocol of Class-1 Generation-2 UHF RFID System", IEEE EIT Conference, May 2010
  8. Li Li and Ken Choi, "SeSCG: Selective Sequential Clock Gating for Ultra-Low Power Multimedia Mobile Processor Design", IEEE EIT Conference, May 2010
  9. Wei Wang and Ken Choi, "Novel Curve Fitting Design Methodology to Optimize Carbon Nanotube SRAM Cell",  IEEE EIT Conference, May 2010
  10. Haiqing Nan and Ken Choi, "Novel CNFET SRAM Cell Design Operating in Sub-threshold Region Using Back-Gate Biasing",  IEEE EIT Conference, May 2010
  11. Kyung Ki Kim, Haiqing Nan, Ken Choi, "Power Gating for Ultra-Low Voltage Nanometer ICs", IEEE ISCAS, May 30 - June 2, 2010
  12. Kyung Ki Kim, Haiqing Nan, Ken Choi, "Adaptive HCI-aware Power Gating Structure", IEEE ISQED, March 22-24, 2010
  13. Kyung Ki Kim, Haiqing Nan, and Ken Choi, "Hybrid MOSFET/CNFET Based Power Gating Structure", IEEE SOCC, Sept 27-29. 2010
  14. Haiqing Nan, Ken Choi, "Novel Ternary Logic Design Based on CNFET", in International SoC Design Conference (ISOCC), pp. 115-118, 2010
  15. Haiqing Nan, Kyung Ki Kim, Wei Wang, Ken Choi, "Dynamic Voltage and Frequency Scaling for Power-Constrained Design using Process Voltage and Temperature Sensor Circuits", International Symposium on Wireless sensor network Technology and Applications (WTA) 2010
  16. Haiqing Nan, Ken Choi, "Novel Soft Error Hardening Design of Nanoscale CMOS Latch", in International SoC Design Conference (ISOCC), pp.111-114, 2010
  17. Sandeep Sriram, Haiqing Nan, Ken Choi, "Dual Loop Hardened Latch Circuit for Low Power Application", in International SoC Design Conference (ISOCC), pp.123-126. 2010
  18. Li Li, Haiqing and Ken Choi, "Effective algorithm for integrating clock gating and power gating to reduce dynamic and active leakage power simultaneously", in International Symposium on Quality Electronic Design (ISQED) 2011
  19. Li Li, Ken Choi, "Activity Driven optimized bus specific clock gating for ultra-low power smart space applications", in International Symposium on Wireless Sensor network Technologies and Applications (WTA) 2010
  20. C. Cho, H Lee, K. Choi and A Zehnder, "Development of micro magnetostrictive wireless controllable actuator", in 55th Conference on Magnetism and Magnetic Meterials, November 14-18, 2010, Atlanta, GA
  21. Sandeep Suhas, Haiqing Nan, and Ken Choi, "Low Power Latch Design in Near Sub-Threshold Region to Improve Reliability for Soft Error", ISQED 2011
  22. Feng Ge, Wei Wang, and Ken Choi, "A Circuit Prototype for Dielectric Polymer Energy Harvesting System", in IEEE Green Technologies Conference, 2011
  23. Jaeik Cho, Ho Joon Lee, Ken Choi, Sangyep Nam and Jongsub Moon, "Visualization of Abnormal Behavior Detection using Parallel Coordinate and Correspondence Analysis", in International Symposium on Advanced in Cryptography, Security and Applications for Future Computing, 2010
  24. Jaeik Cho, Manhyun Chung, Ken Choi, Yangsun Lee, and Jongsub Moon, "Enhanced Security Protocols for EPC Global Gen2 on Smart Grid network", in Enhanced Security Protocols for EPC Global Gen2 on Smart Grid network, 2011
  25. Yu-Chi Tsao and Ken Choi, "Hardware-Efficient Parallel FIR Digital Filter Structure For Symmetric Convolutions", in IEEE International on Circuits and Systems (ISCAS), pp. 2301 June 2011
  26. Yu-Chi Tsao and Ken Choi, "A Simplified Flow for Synthesizing Digital FIR Filter Based on Common Subexpression Elimination", in International SoC Design Conference, pp. 174-177 2010
  27. Arun Ramnath Ramani and Ken Choi, "A Novel 9T SRAM Design in Sub-Threshold Region", in IEEE EIT 2011
  28. Wei Wang, Zhiyuan Yu and Ken Choi, "High SNM 6T CNFET SRAM Cell Design Considering Nanotube Diameter and Transistor Ratio", IEEE EIT 2011
  29. Ho Joon Lee, Haiqing Nan, Kyung Ki Kim and Ken Choi, "High Sensitivity and Low Power Skin Sensor Implementation ans performance Comparison using CMOS and CNFET", IEEE Electro/Information Technology Conference (EIT) 2011
  30. Yu-Chi Tsao and Ken Choi, "Cost Reduction on High-Speed 1D IDCT Architecture based on Time Rescaling", in IEEE EIT 2011
  31. Bohan Lin, Fan Wu, Haiqing Nan, and Ken Choi, "Near-Threshold Low Power Process Monitor for Deeply Scaled CMOS Technology", in IEEE EIT 2011
  32. Zhiyuan Yu, Yinhui Chen, Haiqing Nan, Wei Wang and Ken Choi, "Design of Novel Low Power 6T CNFET SRAM Cell Working in Sub-Threshold Region", in IEEE EIT 2011
  33. Peiwen He, Feng Ge, Wei Wang, Gyungsoo Kang, SooHyun Kim and Ken Choi, "Simulation for Energy Harvesting System Based on Dielectric Electro Active Polymers", in IEEE EIT 2011
  34. Yinhui Chen, Zhiyuan Yu, Haiqing Nan, and Ken Choi, "Ultralow Power SRAM Design in Near Threshold Region using 45nm CMOS Technology", IEEE EIT 2011
  35. Wei Wang, Peiwen He, Setiwan Seokoma, Feng Ge and Ken Choi, "Dielectric Electroactive Polymer (DEAP) Energy Harvesting System Forward Path Design for Different Vibration Input Patterns", in IEEE EIT 2011
  36. Jaeik Cho, Kyuwon Choi, Taeshik Shon, Jongsub Moon, "Enhanced Network Data Set Modeling Method and Its Evaluation Using MIT/LL Data Set", STA 2011 THe 8th FTRA International Conference on Secure and Trust Computing, data management and Applications 2011 28-30 June, 2011 Crete, Greece
  37. Wei Wang, Yuchi Yuan, Peiwen He, Ho Joon Lee, and Ken Choi, "Design Method for 6T CNFET Misalignment Immune SRAM Circuit", IEEE MWSCAS 2011
  38. Li Li, Ho Joon Lee, and Ken Choi, "Power efficient data retention logic design in the integration of power gating and clock gating", IEEE MWSCAS 2011
  39. Sandeep Suhas, Haiqing Nan, Ho Joon Lee, and Ken Choi, "A Novel Dual Edge Triggered Near-Threshold State Rententive Latch Design", IEEE MWSCAS 2011
  40. Ho Joon Lee, Ken Choi, and Kyung Ki Kim, "Sensor Interface Circuit for Artificial Skin Sensor Using CNFET", IEEE MWSCAS 2011
  41. Yu-Chi Tsao and Ken Choi, "Cost-Reduced high speed architecture for Lattice Digital Filters Based on Cut-Set Localization", in proc. of FTRA International Symposium on Wireless Sensor Network Technologies and Applications for Smart Space (WTA) 2011
  42. Li Li, and Ken Choi, "Energy Efficient Encoder Design of Distributed Video Coding for Wireless Video Sensor Network",  in proc. of FTRA International Symposium on Wireless Sensor Network Technologies and Applications for Smart Space (WTA) 2011
  43. Haiqing Nan, and Ken Choi, "Hardened latch design for deeply scaled CMOS technology",  in proc. of FTRA International Symposium on Wireless Sensor Network Technologies and Applications for Smart Space (WTA) 2011

Selected Previous Publications

  • Software Level
  1. K-w. Choi and A. Chatterjee, “Efficient Instruction-level optimization methodology for low-power embedded systems,” Proc. of ACM/IEEE International Symposium on System Synthesis, pp.147-152, Sept. 2001
  2. K-w. Choi, “QoS-based adaptive error control for hybrid (satellite and terrestrial) networks,” GIT-EE-98, Technical Report at Georgia Institute of Technology, 1998

  • System Level
  1. K-w. Choi, Y. S. Dhillon, U. Diril, A. Chatterjee, et. al., "Power-PerformanceTrade-offs in Second Level memory used by as ARM-like RISC Architecture", (one chapter in) Power Aware Computing, Kluwer Academic Publishers, Part IV, Chapter 11, pp 215-228, 2001
  2. K, Puttasuwami, K-w. Choi, A. Chatterjee, et. al, “System level power-performance trade-offs in embedded systems using voltage and frequency scaling of off-chip buses and memory,” Proc. of ACM/IEEE International Symposium on System Synthesis, Oct. 2002
  3. Y. S. Dhillon, U. Diril, K-w. Choi, and A. Chatterjee,"An O(n) supply voltage assignment for low-energy serially connected CMOS modules and a heuristic extension for acyclic data flow graphs", submitted to IEEE Computer Society Annual Symposium on VLSI, 2003
  4. K-w. Choi, A. Chatterjee, et.al., “Software-Hardware delay optimization for ultra-low power operations,” GIT-CC-02-16, Technical Report at Georgia Institute of Technology, 2002

  • Architecture Level
  1. J.C. Park, K-w. Choi, A. Chatterjee, et. al, “Energy minimization of a pipelined processor using a low voltage pipelined cache,” Proc. of 36th Annual Asilomar Conference on Signals, Systems, and Computers, Nov. 3-6, 2002

  • Circuit/Gate Level
  1. K-w. Choi and A. Chatterjee, “HA2TSD: Hierarchical time slack distribution for ultra-low power CMOS VLSI” Proc. of the International Symposium on Low Power Electronics and Design, pp.207-212, 2002
  2. K-w. Choi and A. Chatterjee, “PA-ZSA (Power Aware Zero Slack Algorithm): A graph based timing analysis for ultra low-power CMOS VLSI,” Proc. of PATMOS’2002, pp. 178-187, Sep. 2002
  3. K-w. Choi and A. Chatterjee, “Hierarchical power optimization for SoC (system-on-chip),” GIT-CC-02-02, Technical Report at Georgia Institute of Technology, 2002
  4. K-w. Choi and A. Chatterjee, “HiPOS: Hierarchical Power Optimization Strategy for ultra low-power CMOS VLSI,” submitted to IEEE Transactions of VLSI Systems, 2005
  5. K-w. Choi and A. Chatterjee, “Gate-level power-aware optimization via graph-based timing analysis for ultra low-power CMOS VLSI,” submitted to IEEE/ACM Transactions on Design Automation of Electronic Systems(TODAES), 2005
  6. K-w. Choi, Y. Xu, and T. Sakurai, “Optimal Zigzag (OZ): an effective yet feasible power-gating scheme achieving two orders of magnitude lower standby leakage,” in VLSI Symposium, 2005
  7. K-w. Choi, K.M. Choi and J.T. Kong, “Full-Chip-Level Considerations for Fine-Grained Power-Gating Scheme to Reduce Two Orders of Magnitude Lower Leakage Current,” in ISOCC 2005
  8. K-w. Choi, Jerry Frenkil, “VEDA: Vectorless Event-Driven Approach for Optimal Switch Sizing of Power-Gating Circuits to Reduce Two Orders of Magnitude of Leakage Power,” in SAME conference in Nice, France, Oct., 2006
  • Layout Level
  1. K-w. Choi and A. Chatterjee, “UDSM (ultra deep submicron)-aware post-layout device and interconnect co-optimization for ultra low-power CMOS VLSI,” ISLPED, 2003

 

 

 

 

 

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