Principal advisor

   Dr. Ken Choi

   Kyuwon (Ken) Choi is currently a full professor in the department of Electrical and Computer Engineering in Illinois Institute of Technology. He received the PhD. degree in electrical and computer engineering from Georgia Institute of Technology, Atlanta, USA in 2002. During the PhD. he proposed and conducted several projects supported by NASA (National Aeronautics and Space Administration), DARPA (Defense Advanced Research Projects Agency), NSF (US National Science Foundation), and SRC (Scientific Research Corporation) regarding power-aware computing/communication (PACC). Since 2004, he had been with the Takayasu Sakurai Lab. in the University of Tokyo, Japan as a post-doc research associate, working on leakage-power-reduction circuit techniques.

Dr. Ken Choi was a senior CAD engineer and a technical consultant for low-power system-on-chip (SoC) design in Samsung Semiconductor, Broadcom and Sequence Design prior to joining IIT. In the past, he had eight-year industry experience in the area of VLSI chip design from compiler level to circuit level. Last few years, by using his novel low-power techniques, several processor and control chips were successfully fabricated in deep-submicrometer technology and more than 80 peer-reviewed journals and conference papers have been published. He is now a director of VLSI Design and Automation Lab (DA-Lab) at IIT, a senior member of IEEE, an editor-in-chief of Journal of Pervasive Technologies, guest editor of Springer and Wiley Journals, a TPC member for several IEEE circuit design conferences, and an ex-president in KSEA (Korean-American Scientists and Engineers Association)-Chicago/Midwest chapter and a technical group director for KSEA-HQ now.

Senior Research Associate(Post-Doctoral)

    Dr. Jake Cho

    Education

•  Ph.D. in Information Security, Korea University, 2012
•  M.E. in Information Security, Korea University, 2008

    Experience

•  Senior researcher, Samsung Electronics, 2012-2016
•  Manager, IBM Security, 2016-2020

    Research interests

•  Effective Machine Learning/Pattern Recognition for abnormal detection such as Light-weight Support Vector Machine for vehicle system, Kernel Discriminant Analysis

•  Commercial Network/System security :

  Abnormal behavior analysis for SCADA/Smart-grid network

•  IoT/Mobile security architect and its cloud platform security :

  Secure Boot / Secure OS security protocol, security assessment, secure model design

  Secure Element security protocol, analysis, architect: Android, Tizen & Other mobile OS security analysis, architect

•  Industry/IoT network Security :

  Intrusion Detection System/Intrusion Prevention System

  Network based ID System, Anomaly detection

  Covert Channel in network traffic - analysis of protocol suite : Abnormal Prevention with light-weight

  machine leaning method and research effective method

•  Vehicle Network/System security :

  Abnormal behavior analysis for Embedded vehicle network, system security analysis

    Dr. Heeyoung Cho

    Education

•  Ph.D. in Mechanical Engineering, Nihon University, 1997
•  M.E. in Mechanical Engineering, Nihon University, 1994

    Experience

•  Research Director, Jinbo. Co., Ltd, 2023
•  Vice President, Zein Motors, 2022-2023
•  Sr.Staff Engineer, Korea Intelligent Automotive Parts Promotion Institute, 2021-2022
•  Executive Director, Semisysco.Co.,Ltd, 2017-2021
•  Program Director, Korea Evaluation Institute of Industrial Technology, 2016-2017
•  Program Director, Korea Evaluation Institute of Industrial Technology, 2016-2017
•  Staff Engineer, Hyundai Motor Company, 2003-2016
•  Senior Engineer, TOYOTA Motor Company, 2000-2003
•  Engineer, Samsung Advanced Institute of Technology, 1997-2000

    Dr. Seonghyeon Gong

    Education

•  Ph.D. in Computer Science and Engineering, Seoul National University of Science and Technology, 2022
•  M.E. in IComputer Science and Engineering, Seoul National University of Science and Technology, 2018

    Research interests

•  Security with AI: Cybersecurity-related data analysis techniques using SOTA models such as BERT/GPT3
•  Threat Intelligence Detection: prediction and profiling on cyber threats with analysis related to cyber threat intelligence (CTI).
•  Graph AI: Methodologies to represent and analyze complex correlations of information in cybersecurity using graph model.
•  Blockchain: Scalability issues and solutions in blockchains, including off‑chain, shading, and zero‑knowledge proofs.

Ph.D. STUDENTS

    YoungBae Kim

    Education

• Ph.D. Candidate in Electrical Engineering, Illinois Institute of Technology, U.S.
• M.S. in Electrical Engineering, Illinois Institute of Technology, U.S., 2016

    Research interests

•  High-performance and low-power digital IC design and deep learning
•  Low Power and High speed H/W Design at RT level and system level
•  FinFET and CNFET based Low-Power SRAM design
•  Reliable Device & Circuit Co-Design

    Nader Alnatsheh

    Education

• Ph.D. Student in Electrical Engineering, Illinois Institute of Technology, U.S.
• M.S. in Electrical Engineering, Illinois Institute of Technology, U.S., 2022

    Research interests

•  Design for Low Power/High Speed VLSI Circuits
•  Efficient Hardware for Digital Signal & Image Processing Applications

MASTER STUDENTS

    Krishna Manoj Sampara

    Education

• Pursing M.A.S. in VLSI and Microelectronics, Illinois Institute of Technology, U.S.

    Research interests

•  Low-power VLSI design
•  Lower Node Technology for Integrated circuits

    Jithendra Pulivarthi

    Education

• Pursing M.A.S. in VLSI and Microelectronics, Illinois Institute of Technology, U.S.

    Research interests

•  Low-power/High-speed VLSI design
•  High-performance on scalable SoC applications
•  RTL/HLS (high-level synthesis) system verification/validation
•  CMOS RF integrated circuit design

    Krishna Sahithi Inumula

    Education

• Pursing M.S. in Electrical Engineering, Illinois Institute of Technology, U.S.
• MTech in VLSI DESIGN, Vellore Institute of Technology University, India., 2020

    Experience

•  Validate Engineer, STMicroelectronics,India, 2021-2022

    Research interests

•  Analog layouts of CMOS Technology
•  Physical Verification like DRC and LVS checks
•  Validation of DRC Deck Rule for different technology

    Shubham Havaldar Prajapati

    Education

• Pursing M.S. in Electrical Engineering, Illinois Institute of Technology, U.S.

    Research interests

•  VLSI Design
•  Low power VLSI
•  Power electronics technologies

    Siddharth Chandravadivel

    Education

• Pursing M.A.S. in VLSI and Microelectronics, Illinois Institute of Technology, U.S.

    Research interests

•  Low-power and High-performance VLSI design
•  Reliable Carbon nanotube design for low-power VLSI
•  Low-power solutions for HW/SW co-design
•  Latest trends in FinFET and Nanosheet-based GAAFET

ALUMNI

    Graduates

• Shuai Li (Ph.D, 2019)
• Yunlong Zhang (Ph.D, 2019)
• Qiang Tong (Ph.D, 2017)
• Wei Wang (Ph.D, 2012)
• Li Li (Ph.D, 2012)
• Haiqing Nan (Ph.D, 2011)
• Yu-Chi Tsao(Ph.D, 2011)
• Shreyash Jagdish Patel (M.Eng., 2019)
• Olivier Betschi (M.Eng., 2019)
• Rahaprian Premavathi (M.Eng., 2016)
• Junchao Wang (M.S., 2015)
• Weidong Sun (M.Eng., 2014)
• Chen Wang (M.Eng., 2013)

    Undergraduates

•  George Williams