VLSI Design and Automation Lab, IIT

Principal Advisor

Dr. Kyuwon (Ken) Choi

Dr. Kyuwon (Ken) Choi holding a chip

Education

Kyuwon (Ken) Choi is currently a full professor in the Department of Electrical and Computer Engineering at the Illinois Institute of Technology (IIT). He received his Ph.D. in Electrical and Computer Engineering from the Georgia Institute of Technology in 2003. During his doctoral studies, he proposed and conducted several research projects supported by NASA, DARPA, NSF, and SRC, focusing on power-aware computing and communication (PACC).

From 2004, he was a postdoctoral research associate in the Takayasu Sakurai Laboratory at the University of Tokyo, Japan, where he worked on circuit techniques for leakage power reduction. Prior to joining IIT, Dr. Choi served as a senior CAD engineer and technical consultant for low-power system-on-chip (SoC) design at Samsung Semiconductor, Broadcom, and Sequence Design. He has over eight years of industry experience in VLSI chip design, spanning compiler-level to circuit-level development.

In recent years, several processor and control chips utilizing his low-power techniques have been successfully fabricated in deep-submicrometer technologies. Dr. Choi has authored and co-authored more than 80 peer-reviewed journal and conference publications. He is the Director of the VLSI Design and Automation Laboratory (DA-Lab) at IIT, a Senior Member of IEEE, Editor-in-Chief of the Journal of Pervasive Technologies, and a guest editor for Springer and Wiley journals. He has also served as a Technical Program Committee (TPC) member for multiple IEEE circuit design conferences, President of the KSEA Chicago and Midwest Chapter, and Technical Group Director for KSEA Headquarters.

Senior Research Associates (Post-Doctoral)

Dr. Jake Cho

Dr. Jake Cho

Education

  • Ph.D. in Information Security, Korea University, 2012
  • M.E. in Information Security, Korea University, 2008

Experience

  • Senior Researcher, Samsung Electronics, 2012-2016
  • Manager, IBM Security, 2016-2020

Research interests

  • Effective machine learning and pattern recognition for anomaly detection (for example, lightweight SVM for vehicle systems; kernel discriminant analysis)
  • Commercial network and system security: abnormal behavior analysis for SCADA and smart-grid networks
  • IoT and mobile security architectures and cloud platform security: Secure Boot and Secure OS protocols, security assessment, secure model design; Secure Element protocols and analysis; Android, Tizen, and other mobile OS security
  • Industrial and IoT network security: IDS and IPS, anomaly detection, covert channels, protocol suite analysis; lightweight machine learning for prevention
  • Vehicle network and system security: abnormal behavior analysis for embedded vehicle networks and system security analysis

Dr. Heeyoung Jo

Dr. Heeyoung Jo

Education

  • Ph.D. in Mechanical Engineering, Nihon University, 1997
  • M.E. in Mechanical Engineering, Nihon University, 1994

Experience

  • Sr. Staff Engineer, Korea Intelligent Automotive Parts Promotion Institute, 2021-2022
  • Executive Director, Semisysco Co., Ltd, 2017-2021
  • Program Director, Korea Evaluation Institute of Industrial Technology, 2016-2017
  • Staff Engineer, Hyundai Motor Company, 2003-2016
  • Senior Engineer, Toyota Motor Company, 2000-2003
  • Engineer, Samsung Advanced Institute of Technology, 1997-2000

Dr. Seonghyeon Gong

• Google Scholar

Dr. Seonghyeon Gong

Education

  • Ph.D. in Computer Science and Engineering, Seoul National University of Science and Technology, 2022
  • M.E. in Computer Science and Engineering, Seoul National University of Science and Technology, 2018

Research interests

  • Security with AI: cybersecurity data analysis techniques using state-of-the-art models
  • Threat intelligence detection: prediction and profiling of cyber threats; CTI analysis
  • Graph AI: methods to represent and analyze complex correlations in cybersecurity using graph models
  • Blockchain: scalability issues and solutions including off-chain, sharding, and zero-knowledge proofs

Research Associate (Master Level)

Yatrik Ashish Shah

• Google Scholar

Yatrik Ashish Shah

Education

  • Research Associate, VLSI Design and Automation Lab
  • M.S. in Computer Engineering, Illinois Institute of Technology, U.S.
  • B.S. in Instrumentation and Control Engineering, Government Engineering College, Gandhinagar, India, 2022

Research interests

  • High-performance and ultra-low-power design at RT and system levels
  • Hardware and software co-design for low-power, high-speed machine learning on FPGA

Ph.D. Students

Sai Manohar Vemuri

• Google Scholar

Sai Manohar Vemuri

Education

  • Ph.D. Candidate in Computer Engineering, Illinois Institute of Technology, U.S.
  • M.A.S. in Computer Science, Illinois Institute of Technology, U.S., 2024

Research interests

  • Hardware and software co-design for edge AI: optimizing object detection and segmentation models for efficient execution on edge devices
  • Model compression and optimization: quantization, pruning, knowledge distillation
  • 3D perception and sensor fusion: accelerating LiDAR-based 3D vision and multi-sensor integration for real-time inference on reconfigurable hardware

Achyuth Gundrapally

• Google Scholar

Achyuth Gundrapally

Education

  • Ph.D. Candidate in Electrical Engineering, Illinois Institute of Technology, U.S.
  • B.Tech in Electronics and Communication Engineering, Indian Institute of Information Technology, Chittoor, India, 2022

Research interests

  • Ultra-low-power RT-level power-reduction techniques
  • FinFET and MTCMOS-based circuit design for faster, low-power SRAM
  • Computer-architecture-based out-of-order predictions for RISC-V

Adnan Patel

Adnan Patel

Education

  • Ph.D. Candidate in Electrical Engineering, Illinois Institute of Technology, U.S.
  • M.A.S. in Electrical Engineering, Illinois Institute of Technology, U.S., 2024

Research interests

  • FPGA integration for sensor applications
  • LiDAR sensor data preparation for segmentation and classification
  • GAAFETs integration for CIM in low-power circuit design - SRAM cells

Master Students

Sohan Sai Dasaraju

• Google Scholar

Sohan Sai Dasaraju

Education

  • Pursuing M.S. in Electrical Engineering, Illinois Institute of Technology, U.S.
  • B.Tech in Electronics and Communication, Vellore Institute of Technology, India, 2024

Research interests

  • High-performance and ultra-low-power design at RT and system levels
  • Low-power circuit design for machine learning architectures
  • LiDAR sensor integration for GPU and FPGA applications

Former Research Group Members

Ph.D. Students

M.S. Students

B.S. Students