module stimulus;
   
   // Declare variables for stimulating input
   reg [3:0] YN;
   
   // All outputs declared with wire
   wire      a;
   wire      b;
   wire      c;
   wire      d;
   wire      e;
   wire      f;
   wire      g;


   // Instantiate the design block counter
   seven_segment s1(a, b, c, d, e, f, g, YN);


   // Stimulate the Input Signals
   initial
     begin
        #10 YN = 4'b0000;
        #5 $display("%d %b %b %b %b %b %b %b", YN, a, b, c, d, e, f, g);
        // Notice that the vector YN is displayed as a decimal number

        // Add your test vectors here for extensive test of the circuit
   
     end
   
endmodule // stimulus