// accumulator
// reset=0 -> set acc to 0
// reset=1 -> add "in" to acc

module dff(d, clk, q);
   
   output q;
   input  d, clk;
   reg 	  q;
   
   always @(posedge clk)
     q <= d;
   
endmodule // dff

module accu(in, acc, clk, reset);

   input [7:0] in;
   input clk, reset;
   output [7:0] acc;
   wire [7:0] acc;
   wire [7:0] dff_in;
   
   dff r0(dff_in[0], clk, acc[0]);
   dff r1(dff_in[1], clk, acc[1]);
   dff r2(dff_in[2], clk, acc[2]);
   dff r3(dff_in[3], clk, acc[3]);
   dff r4(dff_in[4], clk, acc[4]);
   dff r5(dff_in[5], clk, acc[5]);
   dff r6(dff_in[6], clk, acc[6]);
   dff r7(dff_in[7], clk, acc[7]);
  
   assign dff_in = reset? 8'b0: acc+in;

endmodule